Analysis of image processing difficulties and processor selection in security applications
Beijing, China (May 26, 2009)-With the improvement of people â€™s quality of life requirements and the global trend of anti-terrorism, and the continuous improvement of digital technology itself, relying on fingerprint recognition, iris recognition, face recognition and other technologies Biometrics solutions and video surveillance solutions are gradually becoming important means to improve the security of individuals, families, businesses and society. The biometrics program mainly includes four steps: image acquisition, image preprocessing, feature sampling, and matching analysis; and the video surveillance program mainly includes image acquisition, image preprocessing, image processing and transmission, image display, and image management. It is not difficult to see that whether it is biometrics or video surveillance, image preprocessing is necessary. In fact, the flexibility, complexity, occupancy of image processing chip resources, and the length of processing time of the image preprocessing algorithm will have a significant impact on the operation of the entire system. Therefore, image preprocessing is a difficult and critical task for the entire security program, which directly determines the accuracy and convenience of subsequent image processing and analysis.
Image preprocessing analysis According to different purposes, image preprocessing can be divided into clear processing of the collected image, preprocessing of the image before recognition, and preprocessing of the image before compression. Among them, the clarification of the collected image mainly includes subsequent correction of the inconsistency of the photosensitive unit of the CMOS or CCD image sensor, the compensation of the difference between the actual environment and the image collected by the sensor (such as backlight), and the removal of the original image collected Noise processing, etc. Although this kind of preprocessing algorithm itself is not difficult, but with the popularity of real-time requirements, especially when the pixels are large, this algorithm still puts high requirements on the processing power of DSP.
The pre-processing before image recognition is very purposeful, and may need to destroy the original pixels and distribution for subsequent feature extraction. The difficulty of this preprocessing algorithm varies depending on the recognition occasion. To synthesize the later identification algorithm part, select the appropriate DSP. The pre-processing before image compression mainly refers to changing YUV422 to YUV420, RGB to YUV, etc. This type of processing often has real-time requirements. If it is implemented in software, it will have higher requirements for processing performance; if it is implemented in hardware, although the processing performance is guaranteed, the hardware cost will increase.
At the same time, according to different applications, image preprocessing can be divided into image preprocessing in biometric applications and image preprocessing in video surveillance applications. For biometric applications, taking fingerprint recognition as an example, the pre-processing mainly includes fingerprint image enhancement, fingerprint image binarization, fingerprint image thinning, and fingerprint image thinning post-processing. The image preprocessing in video surveillance applications mainly refers to the analysis of continuous images output by the image sensor to obtain sufficient information, and through automatic white balance, gamma (Gamma) correction, auto focus, auto exposure, backlight compensation, etc. Improve the actual effect of the image.
Challenges of image preprocessing Whether it is biometrics or video surveillance, its image preprocessing is facing the following challenges: First, users have higher and higher requirements for image quality, and image preprocessing algorithms are becoming more and more complex, so that image preprocessing Processing the main chip processing capacity and storage space put forward more demanding requirements; Second, users have increasingly higher requirements for real-time processing and transmission of images. On the one hand, image preprocessing algorithms are required to be optimized and streamlined as much as possible. The core processing capabilities, internal bus architecture, data transmission capabilities, peripheral interfaces, and overall hardware architecture and instruction set of the image preprocessing main chip put forward higher requirements for the support of the preprocessing algorithm; third, it is different from the image and video codec The algorithm has a unified algorithm standard and a clear evolution roadmap in the industry. The image preprocessing algorithm not only has no unified standard and a clear development direction, even to a large extent, the solution provider is precisely through these "secret" personalized algorithms Come as a magic weapon for market competition. In addition, with the different application fields, the improvement of demand and the evolution of the technology itself, the original algorithm will continue to be upgraded, and new algorithms will continue to emerge, all of which require the image pre-processing chip to have higher flexibility and adaptability. Fourth, for solution providers, not only does the core algorithm that reflects competitiveness need to be protected from illegal reading or copying, but whether it is biometrics or video surveillance, its image data often involves privacy, so it also needs to provide trust. Security guarantee. Both of the above aspects require that the image processing chip must provide a reliable and complete processing platform.
Based on the above challenges, in the selection of the main chip for image preprocessing, the traditional MCU, which is known for its control ability, is not suitable for large and complex algorithm processing; although ASIC has certain advantages in terms of computing speed and power consumption, its High cost, poor flexibility, and not conducive to upgrades and modifications, so it cannot meet the individual flexibility requirements of the preprocessing algorithm; although the FPGA parallel processing architecture has powerful data processing capabilities, the price, power consumption, and development difficulty The shortcomings make it difficult to become the mainstream choice for image preprocessing; DSP has become the mainstream choice for the main chip of image preprocessing with powerful data processing capabilities and software programmability.
In addition to the above challenges, from the perspective of system design, it also faces the following requirements:
First, although image preprocessing and image processing work is huge, engineers do not want to use multiple chips to deal with this matter. The traditional DSP architecture in which the signal processing and control systems are running on different processors has caused headaches for engineers. If image preprocessing and image processing are separated, it will be more difficult for engineers to carry out system development, system joint debugging, and system maintenance. . Therefore, for the main chip DSP in system design, it also faces the requirement of integration-is it possible to realize image preprocessing, image processing, and even system control and other functions on a single chip.
Second, as the complexity of the entire image processing algorithm including preprocessing continues to increase, as the main processor DSP, in addition to providing sufficient hardware processing power, it should also provide special software for the processor. Optimized instruction set to help engineers reduce the difficulty of familiarity with the physical architecture of the processor, maximize the control and play of the characteristics of the processor, and develop a streamlined and optimized image processing algorithm as soon as possible.
Third, in addition to the specially optimized instruction set mentioned above, in the face of increasing complexity of image processing and time-to-market pressure, engineers also expect processor suppliers to share some of their work-for example, to provide special Processor-optimized, low-level image processing software modules that occupy a very small number of clock cycles to help them shorten the image processing algorithm development process and accelerate software migration.
In addition, powerful, user-friendly, and easy-to-learn development tools are also the focus of engineers' requirements in system development, and as the system complexity and module reuse requirements increase, higher requirements are placed on the compatibility of development tools .
The ideal DSP processor is based on the above analysis. The ideal DSP processor for image processing applications must have the following characteristics: strong core processing capabilities; an instruction set specifically for image processing; a low-power hardware architecture that is easy to transfer large amounts of data; High integration; rich software module library; powerful development tools. The following is a specific analysis of the representative series of this type of DSP processor-Blackfin aggregation processor architecture.
The Blackfin DSP processor is based on the Micro Signal Architecture (MSA) jointly developed by ADI and Intel. By combining the advantages of traditional DSP and microcontroller, it takes into account event control and pure algorithm operation processing functions. Its converged single core can provide up to 756MHz processing power, which not only provides a powerful performance guarantee for processing complex preprocessing algorithms, but also provides strong hardware support for image processing and event control of the entire system, allowing engineers to Image preprocessing, image processing, and system control are realized on the chip, which greatly improves the integration of the system.
The hardware architecture of the Blackfin series processors is specifically optimized for image processing. Multiple DMA channels and configurable Cache can well solve the image processing application requirements of large computation and high data throughput. In image processing applications, although the transfer of image data can also be achieved by software, it will consume a large number of CPU clock cycles, making it difficult for DSP's high-speed data processing capabilities. If the DMA is independently responsible for data transfer, after the system kernel initially sets and starts DMA, the DMA controller can directly transfer image data from the PPI interface to the SDRAM memory for storage without kernel involvement, such as Among the computationally intensive algorithms for MPEG or JPEG processing, a flexible DMA controller can save extra data paths. In addition, two-dimensional DMA can also simplify the transfer of macroblocks into and out of external memory, allowing data control to become part of the actual transfer of data, which is very convenient and important for the interleaving and deinterleaving of color space elements. Therefore, this feature of the Blackfin processor effectively solves the speed bottleneck of large-scale image data transmission, and at the same time allows the DSP processor to extract more resources for algorithm processing, which greatly improves the processing capacity of the system.
Moreover, for image processing applications, the Blackfin series of DSPs are constantly strengthening the support of hardware function modules. For example, the latest version of the ADSP-BF54x series of Blackfin processors adds a hardware accelerator for processing superimposed images (Pixel Compositor) and a Extended Video Interface (EPPI), which enables tasks such as color space transformation, scaling, and image overlay to be completed without the need for the processor to participate in the calculation, thereby reducing the processing pressure of the kernel, for higher performance, higher speed images Processing provides more space.
Software characteristics In terms of instruction set, Blackfin series DSP provides a wealth of vector instructions and video instructions for image processing. Among them, vector instructions can implement 16-bit operations (most instructions can complete two 16-bit operations in parallel). Since most of the image processing operations are for 16-bit operations, it is very important to optimize image operations by using these vector instructions properly. Not only do most arithmetic instructions and shift instructions in the Blackfin instruction set have corresponding vector instructions, but there are also special instructions such as addition of symbols, 32-bit to 16-bit conversion, etc. in vector instructions. The rational use of these vector instructions in the assembly optimization of image preprocessing can improve the parallelism of the algorithm and greatly speed up the operation.
Video pixel commands mainly include BYTEOP16P (complete two 8-digit addition operations), BYTEOP3P (complete 16-bit and 8-digit addition operations), BYTEOPIP (complete two 8-digit averaging operations), BYTEOPZP (complete four 8-digit addition operations) Digit average operation), BYTEOP16M (complete two 8-digit subtraction operations), SAA (complete SAD operation), BYTEAPCK (complete 16-digit to 8-digit operation), and BYTEUNAPCK (complete 8-digit to 16-digit operation) Number operation) etc. A video pixel operation instruction can complete 11 types of video pixel operations such as adding, subtracting, adding and subtracting, averaging, or subtracting and calculating the absolute value of 4 pairs of video data components in one cycle. Since the video pixel values â€‹â€‹are generally stored according to 8 bits, the use of video pixel instructions can greatly improve the speed of various video image operations including seeking SAD, pixel interpolation, 8-bit and 16-bit direct conversion, etc.
Security Features In terms of security, ADI â€™s Blackfin Lockbox Secure Technology combines software and hardware protection by providing one-time programmable (OTP) memory and a secure processing mode (Blackfin security mode) to provide developers with the means to implement the above security measures Means, where developers in the public, non-secure, user-programmable area of â€‹â€‹OTP memory can be used to store public keys, so that the system can be authenticated in a controlled and configurable manner. In the private, secure, and user-programmable areas of OTP memory, developers can set up private device assets such as private keys, and maintain the confidentiality and integrity of these device assets. In addition, after using secure mode on the Blackfin processor, the processor can only perform authorized trust codes within the secure processing environment. These include protection of secrets (such as original equipment manufacturer intellectual property rights), verification of device and user identities to protect e-commerce and social networks, and digital copyright (DRM) content protection. So as to provide tailor-made security protection function for each link of image preprocessing scheme.
Software module library support In addition to the above Blackfin DSP's support for image processing in terms of hardware architecture and instruction set, ADI also provides a variety of software modules for image processing, including H.264 Baseline Profile Decoder module, which can be scaled with different Enhanced video post-processing (eVPP) module for input and output size images, JPEG encoder module MPEG-2 Decoder Simple & Main Profile Decoder library, MPEG-4 Simple Profile & Advanced Simple Profile Decoder library, and MPEG-4 Simple Profile & Advanced Simple Profile Video Encoder modules, etc., they are specifically optimized for Blackfin processors and have been strictly verified by the industry. These software modules can greatly reduce the development difficulty of system engineers and significantly improve system efficiency.
In addition, ADI also launched the "Image Tool Box" software package specifically for image processing applications. The software package consists of a series of special modules and is optimized for some common and basic functions of image processing algorithms. It can perform image transformation. , Image analysis and image enhancement, binary image operations and morphological processing and other image processing operations. This software package helps reduce the development difficulty of engineers and accelerate the implementation and optimization of upper-layer algorithms.
Development environment support The VisualDSP ++ development environment for Blackfin series DSP processor development applications and project management mainly includes an integrated compilation and debugging environment (DIDE) with integrated ViusalDSP ++ core; CC / ++ optimized compiler with real-time runtime library; assembly And linker, as well as simulation software and program routines. Among them, the compiler allows program developers to write signal processing and control codes in C or C ++ language, thereby facilitating the development and maintenance of the system. The graphical and user-friendly information exchange interface enables engineers to perform project management, editing, compiling, and debugging programs in the window, and quickly and easily switch between them. In addition, the VisualDSP ++ development tools are also compatible with Green Hills Software â€™s MULTI environment, NI â€™s LabVIEW software, and MathWorks â€™MATLAB and Simulink software, providing a more convenient and relaxed environment for system development and module reuse.
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