SDI is a serial digital interface that is used to transmit uncompressed digital video signals. In the 1980s, SDI was rapidly developed and defined its standards. 3G in 3G-SDI means that the data transmission rate of the SDI signal is 3 Gbits per second. Since HDTV can support a progressive scan of 1920×1080 resolution format of 30 frames per second, 3G can support twice the frequency of the highest frame scan frequency of HD video signals, that is, 3G can support HD signals of 60 frames per second. This is a big difference when watching a dynamic video.
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SMPTE424M defines the physical layer of 3G-SDI and the characteristic performance of such electrical signals. The transmitted signal should have a voltage swing of 800mV, and the rise and fall times must be less than 135ps, allowing some overshoot to exist, but not more than 10%, or 80mV. The definitions of clock jitter and adjustment jitter are specified in SMPTERP 184. The jitter parameters required are less than 2UI and 0.2UI respectively. The adjustment jitter parameter is actually required to be 0.3UI, but SMPTE strongly recommends using the 0.2UI parameter requirement, so this article will use 0.2UI parameter requirements. In the receiver, the input jitter tolerance is in the frequency band of 10 Hz to 297 MHz, from 2 UI to 0.2 UI. Both the output of the transmitter and the input of the receiver should be optimized to guarantee return loss.
In the transmitter, most of the jitter comes from the serializer, and the cable driver adds some jitter. Figure 1 shows a typical block diagram of the transmitter currently in use, which works for HD, SDI, but it does not support 3G-SDI. Since the 20-bit digital video bus has already created EMI problems in HD, and this clock frequency doubles in 3G, EMI problems will be more serious in 3G. In addition, PCB wiring is not a simple task, engineers will face 20 traces at 148.5MHz. The clock signals generated by the FPGA also contain a lot of jitter, so these clocks are not suitable for direct use in the serializer. Since the output jitter of the serializer is increased, it is necessary to add a jitter cancellation circuit or a Genlock circuit to eliminate the jitter. In addition, some serializers also require a clean local clock. These jitter and local clocks not only increase system cost, but also occupy PCB area. Finally, the serializer is an analog signal device that contains a digital processing unit and an analog serial unit, making it difficult to produce low-jitter analog and digital signals. Taking the HD signal as an example, the minimum achievable output jitter is about 115ps or 0.17UI, so if you want to support 3G, you must adopt a completely new structure.
The innovative architecture of NS's SDI serializer and deserializer products provides SDI-3G with low-radiation, low-cost, low-jitter and high-performance solutions using LVDS technology between FPGAs and serializers or deserializers. , thus removing the TTL connection. Because LVDS has very low EMI emissions and power loss, it is ideal for use in handheld products. In addition, the PCB's printed line has been reduced from 20 to 10, making PCB design easier. Since the high-performance PLL phase-locked loop is designed inside the chip, the external local clock and the jitter elimination circuit are no longer needed, so the system cost is significantly reduced, and the board area is saved. Because FPGAs are already in the system and do not require additional cost, most digital signal processing can be done by FPGAs such as CRC and line number insertion, raster, ANC, and EDH insertion. In fact, since the most difficult serial work is now done by the serializer, the level of the FPGA can be reduced. This serialization improves the jitter tolerance of the deserializer by using an excellent analog technology process and a high-precision phase-locked loop, which can reach a minimum of 0.6 UI. Similar to the serializer, we can also integrate similar loops in the deserializer, which can simplify the design and reduce the space, so such a deserializer does not need a local clock, it is a tiny space of 7×7 The millimeter LLP package is shown in Figure 2.
When a signal is transferred from one medium to another, some of the signal will be reflected and the remaining signal will pass through the medium. Both acousto-optic and electromagnetic waves have similar characteristics because the density and characteristics of the medium change as the medium changes. In the principle of the transmission line, the width of the printed circuit line is proportional to its characteristic impedance, so reflection occurs when the signal is transmitted between two different impedance printed circuit lines, and the occurrence of reflection reduces the energy of the signal, affecting The receiver's processing, while the signal to noise ratio will also be reduced. In addition, when the signal is reflected back toward the source, it will be mixed with the original signal to reduce the signal integrity, as shown in Figure 3.
Return loss can be used to measure the pros and cons of two impedance matching. The usual BNC connectors, board traces, cable drivers, output impedance or equalizer impedance are different, so SMPTE strict return loss specifications must be considered in practical applications. The loop loss is a frequency-dependent parameter. As the frequency increases, the parasitic capacitance and inductance become more pronounced, which can degrade the loop losses. NS's SDI series products have good input and output loop loss characteristics, and only need to use a simple small network to match the BNC connector. The most common network can be implemented by connecting a small inductor in parallel with a 75Ω resistor. This matching network should look like a short-circuit line in the DC characteristics, allowing the transmission line impedance to be provided by the terminating resistor; The impedance value of the parasitic capacitance will dominate the frequency condition. At this time, the loop loss compensation network can provide 75Ω impedance as the termination resistor, as shown in Figure 4.
Even if your system can meet the specifications described above, it is not certain that the system is stable and reliable. Unlike analog systems, digital system performance does not slow down, but works without errors until the system is completely damaged. The stability of the system is usually evaluated by a temperament test method, that is, one or more parameters of the digital signal are changed until the digital system is disabled. The most direct temperament test method is to add a cable for the temperament test. Although the video signal is encoded into a digital data stream, the SDI signal is still analog in nature and is still subject to distortion such as attenuation and phase shift. Longer cables are prone to signal loss and phase shift, causing signal distortion. We add an extra cable equalizer to the receiver to compensate for the distortion. In cable transmission, due to the frequency response characteristics of the cable, the signal will produce distortion and phase shift distortion. The equalizer can provide compensation for the distortion signal. We can make the equalization range and noise performance of the receiver by adding a longer cable. Evaluation. This temperament test is especially meaningful when using SDI's pathological signals because it basically mimics the real situation. Serial digital systems are difficult to handle for ill-conditioned signals. In this low-frequency range, one of the areas is used to test the equalizer and the other is used to check the performance of the receiver's phase-locked loop. NS's 3G-SDI equalizer has the ability to equalize the distance of the cable length of 120 meters at 3G. It can be seen from Figure 5 that the 3G-SDI product using NS is easy to meet the SMPTE index.
The signal quality will deteriorate when the SDI signal is transmitted over long distances. To compensate for the loss of long-distance transmission and reconstruct the amplitude of the video signal, an additional cable equalizer is required. However, the equalizer cannot remove the jitter and noise inherent in the signal. Therefore, in order not to cause the jitter of the entire signal link to be accumulated, it is not recommended to use the equalizer output for multi-point transmission. It is recommended to use the clock recovery device to reproduce clean before the transmission. Signal, it is important to note that the clock restorer needs the equalizer to reconstruct the amplitude of the signal and open the eye before regenerating the data. Sometimes when the signal is transmitted between systems, the medium being transferred may be the backplane instead of the cable. In this case, the use of another cable equalizer can compensate for the loss of the signal, but the cost optimization cannot be achieved. Since the backplane is not too long, a passive equalizer is a more ideal solution, which has a very low price and does not consume power.
Clock recoverers and cable drivers are widely used in routers. For example, large routers can consume about 40% of the total power consumption. Sometimes not every output channel is active at the time of application. If these free or unused channels can be turned off, power consumption can be effectively reduced. NS's LMH0303 cable driver features input signal loss alarms and output cable detection to make system design easier. When the input signal is lost, LOS (Loss of Signal) will output a signal to the system to decide whether to shut down the channel of the device. Similarly, the output alarm signal can be used to know if the output cable is not connected or unreliable. These cable drivers and clock restorers are all in deep power saving mode, saving 3mW and 10mW respectively.
Applications
The crosspoint switch is a standard module that is often used in switch circuits and multiplexers, such as in automotive entertainment and navigation systems, with multiple different video signal input sources and multiple different display devices, which need to be in any Any input source is displayed on the display device, and the running and sleeping clocks need to be assigned to different purposes. The first example shown in Figure 6 is a small video router with 2.97G serial video data signals assigned to different locations. The DS25CP104 is a member of the LVDS crosspoint switch family that can handle high speed signals from DC to 3.125Gbps with very low jitter and low power consumption, and each channel can monitor and read LOS via the SM bus. State, LOS can be used to turn off unused channels. Thanks to its very simple SDI device interface, very low jitter and a wide range of data rates, it is widely used in switching and wiring applications. In addition, the device package is small and is a 6×6mm pin arrangement. The second example is the application of the DS25BR204. This is a very simple method of copying 4 signals from 2 optional inputs. It also has a LOS function to optimize power.
For this fast-growing SMPTE424M standard for 3G-SDI transmission, National Semiconductor is the industry's first supplier of complete solutions, including adaptive equalizers, clock restorers, cable drivers, serializers, and deserializers. Devices, cross-point switches, etc. These products meet every application of SDI and are suitable for a wide range of SDI systems. A large cabling system may require all products. Today, with ever-increasing power requirements, some products have a shutdown power consumption of only 3mW, and signal loss alarms and cable connection detection greatly simplify system design.
National Semiconductor and Altera have completed the industry's first video development platform for 3G/HD/SD-SDI systems based on Altera's Cyclone III FPGAs. The solution uses NS's high-performance 3G-SDI signal path, video clock, power manager products and Altera's FPGA products to form a standard and scalable development platform. It includes many featured products such as 3G-SDI products, sync separators in multiple video formats, clock generators, crosspoint switches, LDUs and DC/DC converters, and more.
In addition to Altera, National Semiconductor has partnered with Xilinx to provide a similar development platform. National Semiconductor and Xilinx offer a joint approach to low-cost FPGAs into the high-end AVB market, supporting SD, HD and 3G. Professional video application.
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