At present, with the growth of living and office environment space, the wiring of audio is becoming more and more difficult to achieve in large conference rooms, cars and other places, and the cost is becoming higher and higher. There is an urgent need for wireless transmission of high-quality audio. The transmission rate of CD-quality audio reaches more than 1.5Mbps, so higher bandwidth and distance requirements are put forward for wireless systems.
The ISM 2.4GHz (Industrial ScienTIfic Medical 2.4GHz-2.4835GHz) frequency band is a globally open public frequency band, which has the advantages of high bandwidth and low cost implementation. Selecting the ISM2.4GHz transmission system with high bandwidth characteristics is more suitable for CD-quality audio transmission. Other 2.4GHz systems, such as dental monitoring and WLAN, have shortcomings such as high cost or limited distance, so this system uses a dedicated ISM audio wireless transceiver chip nRF24Z1.
nRF24Z1 provides standard industrial audio I2S interface and S / PDIF digital audio interface, which greatly reduces the transmission cost of audio. And the communication rate is as high as 4Mbps, and the actual data transmission rate is 1.536Mbps, which ensures the lossless transmission of audio with a sampling rate of 16bit at a sampling rate of 48kbps.
1 Chip introduction
nRF24Z1 is a CD-quality wireless digital audio transmission and receiving chip launched by Nordic in Norway. It works in the ISM 2.4GHz band. The maximum output power of the chip is + 0dBm, and the receiving sensitivity is -83dBm. It integrates PLL, clock control and recovery module, TDM QoS module, GFSK module, I2C interface, SPI interface, RF LNA and PA, etc., and integrates two industrial audio standard interfaces, I2S and S / PDIF. I2S interface can be directly connected with various audio A / D, D / A, and S / PDIF can be directly connected with various surround sound equipment.
The radio frequency working mode of the chip is GFSK, Gaussian frequency offset keying. In point-to-point wireless communication, this method is widely used, and the bit error rate is low.
To ensure a low bit error rate in communications, the chip also uses a QoS service quality strategy. Strategies include two-way communication mechanism and response strategy (time division duplex), data integrity strategy and CRC error detection, adaptive frequency hopping, and offline search reconnection strategy.
The two-way communication mechanism and response strategy can be seen in Figure 1. The communication from ATX to ARX is an audio channel, while the communication from ARX to ATX is a control channel. The information of the control channel includes simultaneous transmission information, register information, and pin status information.
The QoS part includes data integrity strategy and CRC error detection. It is completely implemented in hardware. The frame sent by the audio channel includes multiple packets. Each packet is composed of an RF address, valid audio data, and several CRC bits. When the receiving end receives After the Packel's CRC is checked, it will send back information to ATX through the control channel. If the CRC check is incorrect, the sender will retransmit the incorrect packet or packets in the next frame.
Adaptive frequency hopping is an important means of anti-interference, which is discussed in detail in Section 2.4 of this article.
Offline search and reconnection is a measure to ensure the reliability of the connection. When the connection is lost, the transmitter automatically searches according to the RF pattern. Each channel is searched for a period of time. Similarly, the receiver also monitors on each channel. Once the connection is established, the lock At the same time, the channel hops in sequence according to the frequency hopping pattern.
The initial configuration of the chip is completed by EEPROM or MCU through SPI, I2C interface. Whether the chip is in transmit mode or receive mode determines the level of the South MODE pin.
nRF24Zl adopts QFN36 package, all pin lists can refer to the chip documentation, and the pins related to operating the chip are shown in Table 1.
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