ASIC designs are continuously growing in size and complexity, and with the advancements in FPGA capacity and performance, approximately two-thirds of these designs can now be modeled using a single FPGA. However, the remaining one-third—equivalent to about 1/9 of all ASIC designs—still require a multi-FPGA prototype board to meet their complexity and scale.
In the past, ASIC design teams had limited options and often resorted to building custom multi-FPGA prototype boards. Today, however, off-the-shelf multi-FPGA prototyping solutions from companies like Synplicity’s partners offer a more efficient alternative. When paired with the right design tools, these systems can significantly reduce verification time by weeks and save tens of thousands of dollars in NRE costs that would otherwise be incurred through custom development.
This article explores the primary techniques used in ASIC verification, compares the pros and cons of custom versus off-the-shelf multi-FPGA prototyping boards, and introduces the most advanced partitioning and synthesis tools available for validating large-scale designs—whether using internally developed or commercially available boards.
**Alternative Verification Technologies**
Modern high-end ASICs, such as those found in mobile devices, communications systems, graphics processors, and signal processing units, often integrate multiple CPU and DSP cores along with hardware accelerators, peripherals, interfaces, and memory management units. For the purpose of this discussion, the term “ASIC†includes ASSPs and SoCs.
To meet market demands, it is crucial to develop, port, integrate, debug, and verify embedded software as early as possible during the design phase. However, RTL-based verification of an ASIC and its embedded software remains one of the most time-consuming and challenging aspects of the design process. Industry data shows that 70% of today’s ASIC designs require rework, which not only increases costs but also risks missing critical market windows and damaging a company’s reputation.
The three main verification options available to ASIC designers are simulation, hardware-based simulation, and FPGA prototyping.
*Simulation: Software-based simulation is widely used but runs at least six to ten orders of magnitude slower than actual ASIC hardware, making it inefficient for complex designs. It typically operates at just a few Hz, limiting its usefulness for full system verification.
*Hardware-Based Simulation: While faster than software simulation, hardware-based simulators still run at least three orders of magnitude slower than real ASIC speed, often operating between 500 KHz and 2 MHz. These systems are expensive, with costs ranging from 25 cents to a dollar per equivalent gate.
*FPGA Prototyping: This approach offers much higher speed, allowing designs to run at 10–80 MHz, which matches real-time ASIC performance. Using off-the-shelf multi-FPGA boards combined with the right tools can cut weeks off verification time and save significant NRE costs compared to custom designs.
**Fully Custom vs. Off-the-Shelf Prototyping Boards**
Five years ago, most multi-FPGA prototyping systems were custom-built. Today, there are numerous ready-to-use multi-FPGA prototyping platforms available on the market. The traditional hardware simulation market is valued at around $100 million annually, while the off-the-shelf FPGA prototyping market has grown to nearly 75% of that size.
Many engineers believe that custom boards offer better performance, easier real-world interfacing, and lower project costs. However, in reality, designing a custom multi-FPGA board is extremely complex and time-consuming. For example, the DN8000K10 board from Dini Group, a Synplicity partner, took nine months to design and required six layout engineers working in two shifts. The final product is a 28-layer board capable of handling up to 24 million ASIC gates, with inter-chip communication at 350 MHz using LVDS technology.
Such high-level designs are beyond the capabilities of automated routing tools, requiring manual pin selection and path connections. As a result, custom multi-FPGA boards are rarely superior to off-the-shelf alternatives in terms of performance, cost, or time-to-market.
**Manually Partitioning and Synthesizing Multi-FPGA Designs**
Manual partitioning involves translating the original RTL code into a format suitable for FPGAs, which can lead to synchronization issues and functional discrepancies between the prototype and the final ASIC. Engineers often group functional modules and assign them to different FPGAs, but this process is time-consuming and error-prone.
Even with modern tools that support RTL-level partitioning, engineers still face challenges in estimating resource usage across multiple FPGAs. They must repeatedly adjust groupings, analyze results, and make changes, leading to many iterations.
I/O limitations further complicate the process, as some designs may consume all available I/O pins on an FPGA while only utilizing a small portion of the internal logic. To overcome this, engineers may need to replicate logic across multiple FPGAs or redistribute I/O groups, which adds to the complexity.
With each FPGA having over 1,000 pins, managing connections manually becomes a daunting task. Tracking module assignments and cross-FPGA connections requires meticulous documentation, which is both time-consuming and prone to errors.
Leave some time for good sound, perfect sound quality is in your ears. High quality, high enjoyment. The beautiful melody, the beating notes, the magic sound bridges the rhythm of the music, and the experience is unique when you are in the graceful melody.We have the perfect after-sales service and technical support. Look forward to your cooperation!
Single Business Earphone,Handsfree Earphone,Gaming Earphone,True Wireless Headset
Shenzhen Ruidian Technology CO., Ltd , https://www.wisonen.com