Detailed analysis based on I2C bus signal timing

The I2C bus is considered to be in an idle state when both the SDA (Serial Data) and SCL (Serial Clock) lines are high. During this time, the output FETs of all connected devices are turned off, allowing the lines to be pulled up to a high level by external pull-up resistors. This idle condition ensures that no device is actively driving the bus, making it available for communication.

A start signal is generated when the SCL line is high and the SDA line transitions from high to low. This negative edge on the SDA line marks the beginning of a data transfer and is initiated by the master device. Importantly, the start condition must occur only when the bus is idle, as it serves as a timing signal rather than a static level. Similarly, a stop signal is created when the SCL line remains high while the SDA line transitions from low to high, signaling the end of a transmission. Both the start and stop conditions are active signals, not static levels, and are also generated by the master.

When a master wants to continue communicating without releasing the bus after a data exchange, it uses a repeated start (Sr) condition. This allows the master to maintain control of the bus, preventing other masters from taking over during the process. The Sr condition acts as both an end to one transmission and a start to another, ensuring continuous control. If a stop condition is not sent, the bus remains busy, and the next operation can proceed without interruption.

Data is transferred serially over the I2C bus, with each bit synchronized to a clock pulse on the SCL line. While SCL is high, the SDA line must remain stable—low for a '0' and high for a '1'. Changes in the SDA level are only allowed when SCL is low, ensuring proper timing and synchronization. This edge-triggered mechanism guarantees accurate data transfer between devices.

Each byte of data is followed by an acknowledgment (ACK) or non-acknowledgment (NACK) bit. The receiver pulls the SDA line low for an ACK, indicating successful reception, or leaves it high for a NACK, signaling an error. This feedback mechanism helps ensure reliable communication. If the master receives a NACK, it may send a stop condition to terminate the transfer and release the bus.

If a delay is needed between data bytes, the master can hold the SCL line low, effectively pausing the communication. Once released, the bus resumes, giving the slave enough time to process or prepare the next byte. This wait state is commonly used during interrupt handling or processing tasks, allowing the system to manage data flow efficiently.

In rare cases, if the entire bus needs to be blocked, any device can hold the SCL line low, effectively freezing the bus until it is released. This is useful in situations where communication must be temporarily halted. However, such actions should be used carefully to avoid disrupting ongoing transactions.

Bus arbitration is a critical feature of the I2C protocol, especially when multiple masters are present. When two or more masters attempt to take control simultaneously, arbitration occurs on the SDA line. If a master sends a high level while the bus is low, it loses arbitration and stops transmitting. This ensures that only one master controls the bus at a time, preventing conflicts and data corruption.

Clock synchronization is handled through the logical AND of all devices connected to the SCL line. The lowest clock period determines the duration of the SCL low phase, while the shortest high period sets the high phase. This ensures that all devices operate in sync, even if they have different internal clock speeds. As a result, the I2C bus maintains consistent timing across multiple devices.