The performance of the multi-mode RS coding algorithm is analyzed by simulation. The effectiveness of the algorithm in the L-DACS1 system is verified by FPGA. The results show that the multi-mode RS encoder can adjust the mode in real time and perform error control efficiently and stably. , to meet the requirements of L-DACS1 high-speed transmission remains stable.
0 Preface
In order to address the high communication speed requirements and high bandwidth requirements brought about by the growth of ground-to-air data transmission services, ICAO selected L-band aeronautical digital communication system (L-DACS) as the future broadband aviation data link for civil aviation. Transmission scheme. Europe EUROCON-TROL proposes the Future Aeronautical Communication System (FAC), the L-band digital aeronautical communication system types 1 and 2 (L-DACS1 and L-DACS2). L-DACS1 is an aeronautical communication system using Orthogonal Frequency Division Multiplexing (OFDM) technology. It operates in the aeronautical L-band of 960~1 024 MHz and is designed to meet the aeronautical communication requirements for the next 20 years and longer.
In L-DACS1, due to the noise and distortion of the channel and the influence of Doppler shift, the transmitted information causes distortion and signal decision errors, and different types of data need to be transmitted at different rates, so multiple uses are required. Mode channel coding to reduce the bit error rate. RS coding is an excellent error correction code, and its error correction capability and coding efficiency are the highest in linear block codes. It can not only correct random errors, burst errors, and a combination of the two, but can also be used to construct other code classes. Therefore, RS coding is an important part of the current L-DACS1.
1 RS encoder principle
The RS(n, k, t) code is usually represented by three parameters: n, k, and t. among them:
n represents the length of the codeword; k represents the length of the information segment; t represents the number of correctable error symbols. RS (16, 4, 1), RS (21, 19, 1), RS (24, 22, 1), RS (32, 28, 2), RS (43, 39, 2) are used in the L-DACS1 protocol. , RS (49, 45, 2), RS (66, 60, 3) and RS (74, 66, 3) eight modes.
Taking RS(16,4,1) as an example, the generator polynomial of RS(16,4,1) is generally selected according to equation (1):
First calculate the quotient h(x) and the remainder r(x) n - kd(x) g(x) =h(x)g(x) + r(x) , and take the remainder r(x) as the checksum Word, then let c(x) = xn - kd(x) + r(x), placing the information bits in the first half of the codeword, and the supervised bits in the second half of the codeword, so that there is equation (2):
Therefore, the codeword polynomial c(x) must be divisible by the generator polynomial g(x). If the receiver detects that the remainder is not 0, it can judge that the received codeword has an error. The RS encoder structure is shown in Figure 1.
Its working principle is as follows:
(1) Registers R0 - R2t - 1 are all cleared. The switch turns on point A, and then the information bit is divided into two-way transmission circuit, one way is directly sent to C(x), and one way is sent to the dividing circuit and shifted. One byte per clock; (2) All information bits are input at the end of k clocks, and the division function is completed. At this time, the coefficient of the residual r(x) is reserved in the shift register, which is the check bit of the RS code; (3) When the k+1 clock arrives, the switch turns on the point B. The data in the register is sequentially shifted out and sent to the channel. After 2t clocks have passed, the data is completely removed, and 2t check digits are obtained. These 2t parity bits follow the original k information bits to form an RS(n, k, t) code output. This completes the encoding of the RS code; (4) The registers R0 ~ R2t - 1 are all cleared, and steps (1) ~ (3) are repeated to complete the encoding of the next set of RS codes.
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